Basically, a DRAM is an integrated circuit that stores data in binary form (e.g., “1” or “0”) in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, a high logic level is approximately equal to the power supply voltage and a low logic level is approximately equal to ground.
The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a wordline that interconnects cells on the row with a common control signal. Similarly, each column includes a bit line that is coupled to at most one cell in each row. Thus, the word and bit lines can be controlled so as to individually access each cell of the array.
To read data out of a cell, the capacitor of a cell is accessed by selecting the wordline associated with the cell. A complementary bit line that is paired with the bit line for the selected cell is equilibrated to an equilibrium voltage. This equilibration voltage (Veq) is typically midway between the high Vdd and low Vss (typically ground) logic levels. Thus, conventionally, the bit lines are equilibrated to one-half of the power supply voltage, Vdd/2. When the wordline is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage onto the bit line, thus changing the voltage on the bit line. A differential amplifier, conventionally referred to as a sense amplifier, is then used to detect and amplify the difference in voltage on the pair of bit lines.
FIG. 1 represents a conventional memory architecture wherein in order to correctly read a data item from a memory cell of a memory array, a current read from a cell of an addressed memory matrix AM is compared at a sense amplifier SA0-SA7 of a sense amplifier array SAA to a current read from a cell of a reference memory matrix RM that serves in particular to compensate for unknown offset values that are due to irregularities in the fabrication process.
In order to reduce the surface area of a memory, a stacking technique, so-called “staggering” technique, is conventionally used to take into account the pitch difference in between the sense amplifier and the cells. Several sense amplifiers SA0-SA7, generally 4 or 8 as shown in FIG. 1, are therefore staggered one behind each other in the longitudinal direction of the bit lines, such as the bit lines BL2 and bBL2 (complementary to BL2) coupled to sense amplifier SA2.
The architecture of FIG. 1 is disadvantageous in that a bit line and its complementary run over all the staggered sense amplifiers. This leads to a congestion of the space available as metal-0 (metal used for the bit lines) indeed covers 100% of the sense amplifiers.
Moreover, addressing a specific cell of the memory necessitates row and column address buses built from metal tracks, generally metal-1 tracks. When 64 column address buses are used to decode the sense amplifiers of the sense amplifier array, around 100 metal-1 tracks need to be present for power supplies, control commands, I/Os and decoding (64 tracks for this latest group). But in the near future, there needs to be much more focus of the core circuits of a DRAM, especially on the sense amplifier. Indeed, with introduction of Fully Depleted Silicon On Insulator (FDSOI) technology or introduction of high-k/metal gate, devices will get smaller and the metal lines would likely become the limiting factor, not any more the size of the devices. It is therefore understood that 100 metal-1 tracks are far too many for such smaller devices.
FIG. 2 shows another memory architecture that helps limiting the available space congestion. In this architecture, the sense amplifiers array is split into pairs of staggered sense amplifier banks SABe, SABo and the bit lines adopt an interleaved arrangement whereby bit lines alternate in the lateral direction of the wordlines WL between a bit line BL0, bBL0, BL2, bBL2 coupled to a sense amplifier SA0, SA2 of the first bank SAB0 of the pair and a bit line BL1, bBL1 coupled to a sense amplifier SA1 of the second bank SAB1 of the pair. The alternative arrangement of the bit lines result in interconnect spaces available in each sense amplifier bank of the pair parallel to the bit lines. Taking bank SABe as an example, interconnect space is available in between bit lines BL0, bBL0 and bit lines BL2, bBL2. Taking bank SABo as an example, interconnect space is available before bit lines BL1, bBL1. With this alternative arrangement, metal-0 now covers only 50% of the sense amplifiers. With relaxed constraints on the sense amplifiers, the layout is easier.
On the other hand, this architecture necessitates dividing the memory cells array into sub-arrays, which results on the top and bottom sub-arrays being only half-used. Moreover, when 64 column address buses CAB are used (32 buses dedicated to each of the sense amplifier sections), around 140 metal-1 tracks needs to be drawn (around 70 per sense amplifier section). The architecture of FIG. 2 therefore also suffers from the high number of column address buses.
Accordingly, there is a need for improved memory architectures and these are now provided by the present invention.